Although applicable, in principle, to any desired semiconductor memory cells, the present invention and the problem area on which it is based are explained with regard to nonvolatile semiconductor memory cells using silicon technology.
FIG. 2 shows a diagrammatic illustration of the construction of a known nonvolatile memory cell using silicon technology.
In FIG. 2, reference symbol 1 designates a silicon semiconductor substrate of the p-conduction type, into which an n+-type source region S and an n+-type drain region D are introduced. A channel region CH lies between the source region S and the drain region D. A tunnel oxide TO is provided above the channel region CH, a floating gate FG being situated in turn above said tunnel oxide. A coupling oxide KO is provided on the floating gate FG, a control gate CG being situated above said coupling oxide.
During operation of this known nonvolatile memory cell, charge carriers are moved for tunneling through the tunnel oxide TO by the application of an external voltage between the control gate CG and the channel or the source/drain region S, D. In this case, the voltage of the control gate CG is transmitted capacitively via the coupling oxide KO to the floating gate FG. The present charge state of the floating gate FG determines the threshold voltage of the transistor, which ultimately comprises the stored information.
Competitiveness with regard to costs and performance of nonvolatile memory arrangements can only be ensured by advancing miniaturization. At the present time, internal voltages of up to 19 V are required in order to program or erase the known nonvolatile cells, as illustrated, for example, in FIG. 2. In order to handle voltages of this order of magnitude, it is necessary to expend a relatively large amount of chip area for the insulation (e.g. triple wells, “channel stop” counter-implantations, withdrawn diffusion regions, laterally enlarged insulation) and the internal voltage generation (charge pumps).
Increasing miniaturizations of the technologies of nonvolatile memories (flash, EEPROM) can only be achieved by lowering the programming voltage. The latter in turn is dependent on the coupling capacitance between the floating gate FG and the programming line (word line) or the control gate CG. A maximum coupling capacitance is desirable in this connection.
Furthermore, in the case of present-day memory generations, an integration between RAM memories (Random Access Memories) and NVM memories (nonvolatile memories) has never been seriously considered before on account of the complexity of the fabrication processes. Mixed production of DRAM and NVM technologies on a common equipment plant would currently require huge outlays with regard to equipment conversion and would be accompanied by poor equipment capacity utilizations and an increased outlay for production planning and process support.
The object of the present invention is to specify an improved semiconductor memory cell and a corresponding fabrication method, the coupling capacitance being increased.